COMPUTER ORGANIZATION AND ARCHITECTURE (COA), B.E. Computer Science (CS), Semester 4, May 2009.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA),

B.E. Computer Science (CS), Semester 4, May 2009.

Con.2874-09

VR-3324

(3 Hours)

[Total Mark: 100]

N. B.: (1) Question no 1 is compulsory.

(2) Solve any four questions out of remaining.

(3) Draw neat labelled diagram wherever necessary.

1. (a) Explain with suitable example the difference between computer architecture and computer organization. --- (5 Marks)

(b) Define the following terms: --- (5 Marks)

i. Memory Access Time (MAT)

ii. Memory Cycle Time (MCT)

iii. Spatial locality of reference

iv. Temporal locality of reference

v. Cache block.

(c) Explain IEEE format for floating point number representation. --- (10 Marks)

2. (a) Explain and solve the following problem using by restoring division algorithm? Hence divide (163)₁₀ with (11)₁₀. --- (10 Marks)

(b) A 32- bit computer has 32bit memory address. It has 8 KB of cache memory. The computer follows four – way set associative mapping. Each line size is 16 bytes. Show the memory address format and cache memory organization. --- (10 Marks)

3. (a) What is memory interleaving ? Discuss various memory interleaving techniques. --- (10 Marks)

(b) Explain the general organization of CPU? State the function of following CPU registers. --- (10 Marks)

i. MAR (Memory Address Register)

ii. MDR (Memory Data Register)

iii. IR (Instruction Register)

iv. PC (Program Counter)

v. SP (State Pointer).

4. (a) What is Virtual memory? Explain how paging is useful in implementing virtual memory? --- (10 Marks)

(b) Define “(Input / Output) I/O Module ?” State the difference between programmable and non programmable device? Explain in brief DMA data transfer techniques with diagram. --- (10 Marks)

5. (a) Define the term “Soft wired” and “hard wired”. Explain nano – programming. --- (10 Marks)

(b) What is “Micro program” ? Write a Micro program using RTL (register transfer language) notation for the following arithmetic operation. --- (10 Marks)

(i) SUB R1, R2 i.e R1 ßR1- R2

(ii) MUL R1, R2 i.e R1 ßR1*R2

6. (a) Explain in brief about SPARC processor ? Draw and explain in brief n – bit windows architecture of SPARC processor? --- (10 Marks)

(b) Explain the Flynn’s Classification in detail? --- (10 Marks)

7. (a) What is pipelining ? Show that K stage pipe lined processor has k times speed up compared to a non pipe lined systems. --- (10 Marks)

(b) Explain wave front array with suitable example? --- (10 Marks)