COMPUTER ORGANIZATION AND ARCHITECTURE (COA), B.E. Computer Science (CS), Semester 4, December 2009.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA),

B.E. Computer Science (CS), Semester 4, December 2009.

Con.5702-09

SP-7362

(3 Hours)

[Total Mark: 100]

N. B.: (1) Question no 1 is compulsory.

(2) Solve any four questions out of remaining.

(3) Draw neat labelled diagram wherever necessary.

1. (a) Explain Vonnewmann model in detail. --- (5 Marks)

(b) Define the following terms microinstruction, micro operation, micro program. --- (5 Marks)

(c) Explain with suitable example Booth’s Algorithm for signed Multiplication. --- (10 Marks)

2. (a) Explain in detail characteristic of RISC and CISC. --- (10 Marks)

(b) Explain restoring division method, Hence perform 17/3. --- (10 Marks)

3. (a) What is the difference between pipelining and parallelism? Explain the Flynn’s Classification in detail.--- (10 Marks)

(b) Explain in brief about SPARC processor. Draw and explain in brief n – bit windows architecture of SPARC processor. --- (10 Marks)

4. (a) How many 128 bytes RAM chips are required to provide a memory of 2048 bytes? Show details of connection, clearly indicating address, data and decoder configuration.--- (10 Marks)

(b) Explain the different RAID levels. --- (10 Marks)

5. (a) Explain page replacement algorithm. Find out page fault for following string using LRU method. --- (10 Marks)

6   0   12   0   30   4   2   30   32   1   20   15

(Consider page frame size = 3)

(b) Explain the interleaved memory in detail. --- (10 Marks)

6. (a) What is Cache coherence ? Explain Cache coherence strategies in single processor and multiprocessor systems. --- (10 Marks)

(b) Write short notes on any two: - --- (10 Marks)

(i) DMA

(ii) Programmed I/O

(iii) Interrupt Driven I/O

7. (a) Explain systolic processor with suitable example.---- (10 Marks)

(b) What is pipelining? Explain six stage CPU instruction pipeline. --- (10 Marks)

COMPUTER ORGANIZATION AND ARCHITECTURE (COA), B.E. Computer Science (CS), Semester 4, May 2009.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA),

B.E. Computer Science (CS), Semester 4, May 2009.

Con.2874-09

VR-3324

(3 Hours)

[Total Mark: 100]

N. B.: (1) Question no 1 is compulsory.

(2) Solve any four questions out of remaining.

(3) Draw neat labelled diagram wherever necessary.

1. (a) Explain with suitable example the difference between computer architecture and computer organization. --- (5 Marks)

(b) Define the following terms: --- (5 Marks)

i. Memory Access Time (MAT)

ii. Memory Cycle Time (MCT)

iii. Spatial locality of reference

iv. Temporal locality of reference

v. Cache block.

(c) Explain IEEE format for floating point number representation. --- (10 Marks)

2. (a) Explain and solve the following problem using by restoring division algorithm? Hence divide (163)₁₀ with (11)₁₀. --- (10 Marks)

(b) A 32- bit computer has 32bit memory address. It has 8 KB of cache memory. The computer follows four – way set associative mapping. Each line size is 16 bytes. Show the memory address format and cache memory organization. --- (10 Marks)

3. (a) What is memory interleaving ? Discuss various memory interleaving techniques. --- (10 Marks)

(b) Explain the general organization of CPU? State the function of following CPU registers. --- (10 Marks)

i. MAR (Memory Address Register)

ii. MDR (Memory Data Register)

iii. IR (Instruction Register)

iv. PC (Program Counter)

v. SP (State Pointer).

4. (a) What is Virtual memory? Explain how paging is useful in implementing virtual memory? --- (10 Marks)

(b) Define “(Input / Output) I/O Module ?” State the difference between programmable and non programmable device? Explain in brief DMA data transfer techniques with diagram. --- (10 Marks)

5. (a) Define the term “Soft wired” and “hard wired”. Explain nano – programming. --- (10 Marks)

(b) What is “Micro program” ? Write a Micro program using RTL (register transfer language) notation for the following arithmetic operation. --- (10 Marks)

(i) SUB R1, R2 i.e R1 ßR1- R2

(ii) MUL R1, R2 i.e R1 ßR1*R2

6. (a) Explain in brief about SPARC processor ? Draw and explain in brief n – bit windows architecture of SPARC processor? --- (10 Marks)

(b) Explain the Flynn’s Classification in detail? --- (10 Marks)

7. (a) What is pipelining ? Show that K stage pipe lined processor has k times speed up compared to a non pipe lined systems. --- (10 Marks)

(b) Explain wave front array with suitable example? --- (10 Marks)

COMPUTER ORGANIZATION AND ARCHITECTURE (COA), B.E. Computer Science (CS), Semester 4, May 2013.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA),

B.E. Computer Science (CS), Semester 4, May 2013.

Con.6595-13.

GS-6621

(3 Hours)

[Total Mark: 100]

N. B.: (1) Question no 1 is compulsory.

(2) Attempt any four questions out of remaining six questions.

(3) Assume suitable data wherever necessary.

(4) Answer to each new question to be started on fresh page.

1. (a) Explain different Instruction formates with suitable example. --- (10 Marks)

(b) Define following terms: - --- (10 Marks)

(i) Computer Organization

(ii) Computer Architecture

(iii) MDR

(iv) PC

(v) SP

2. (a) Explain Instruction cycle with interrupt executive in detail. --- (10 Marks)

(b) Compare and explain static and dynamic data flow computers. --- (10 Marks)

3. (a) Explain IEEE- 754 formates. --- (10 Marks)

(b) Explain cache memory mapping with pipelined processor. --- (10 Marks)

4. (a) Explain Micro-programmed control unit in detail. --- (10 Marks)

(b) Explain 6- stages Instruction execution with pipelined processor. --- (10 Marks)

5. (a) Explain types of memories based on the hierarchy of speed and size. – (10 Marks)

(b) Define “(Input/Output) I/O Module”. State the difference between Programmable and Non – programmable devices with suitable examples. --- (10 Marks)

6. (a) Compare RISC and CISC processors. --- (10 Marks)

(b) Explain Interleaved Memory with low- order and high- order Interleaving. --- (10 Marks)

7. Write short notes on any four of the following: ---- (20 Marks)

a) RAID Memory

b) Booth’s Algorithm

c) MIMD and SIMD

d) Paging and Segmentation.

e) Page Replacement Algorithm.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA), B.E. Computer Science (CS), Semester 4, December 2012.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA),

B.E. Computer Science (CS), Semester 4, December 2012.

Con.7412-12

KR-3632

(3 Hours)

[Total Mark: 100]

N. B.: (1) Question no 1 is compulsory.

(2) Attempt any four questions out of remaining six questions.

(3) Draw neat labelled diagram wherever necessary.

(4) Answer to each new question to be started on fresh page.

1. (a) Explain Van- Neumann Architecture. --- (6 Marks)

(b) Compare Computer Organization and Computer Architecture with Example. --- (4 Marks)

(c) Explain different Mapping techniques of cache Memory. --- (10 Marks)

2. (a) Compare and contrast DMA, programmed I/O and Interrupt driven I/O. ---(10 Marks)

(b) Compare SRAM and DRAM. ---(5 Marks)

(c) Compare RISC and CISC. --- (5 Marks)

3. (a) Explain design of control unit with respect to Soft wired and Hardwired approach. --- (10 Marks)

(b) Explain IEEE-754 standard formates to represent floating point numbers. --- (10 Marks)

4. (a) What is cache coherency? Explain different protocols to solve cache coherency. --- (10 Marks)

(b) Explain Non- Restoring division algorithm for performing 19/4. --- (10 Marks)

5. (a) Explain multiplication of signed numbers – 13* - 5 using Booth’s algorithm. --- (10 Marks)

(b) What is virtual memory? Explain role of paging and segmentation in virtual memory. --- (10 Marks)

6. (a) Explain SPARC processor in detail. --- (10 Marks)

(b) What is difference between pipelining and parallelism? Show that k – stage pipelined processor has k – times speed up as compared to non- pipelined system. --- (10 Marks)

7. Write short notes on following any four: ---- (20 Marks)

(a) Wave front Array

(b) RAID Memory

(c) Static and dynamic dataflow computer

(d) Systolic Processor

(e) I/O Processor and I/O Channels

(f) Characteristics of two level memory.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA), B.E. Computer Science (CS), Semester 4, May 2012.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA),

B.E. Computer Science (CS), Semester 4, May 2012.

Con.4795-12

GN-9323

(3 Hours)

[Total Mark: 100]

N. B.: (1) Question no 1 is compulsory.

(2) Attempt any four questions out of remaining six questions.

(3) Assume suitable data wherever necessary.

1. (a) Consider a cache (M1) and memory (M2) hierarchy with the following characteristics: --- (10 marks)

M 1 : 16K words, 50 ns access time

M 2 : 1 M words, 400 ns access time

Assume 8 words cache block and set size of 256 words with set associative mapping.

1. Show the mapping between M 1 and M 2.
2. Calculate the effective access time with a cache hit ratio of h = 0.95

(b) What do you mean by Fetch cycle, Instruction Cycle, Machine Cycle, and interrupt acknowledgement cycle? Explain in brief. --- (10 Marks)

2. (a) Multiply (-7) with (3) by using Booth’s multiplication. Give the flow table of multiplication. --- (10 Marks)

(b) What is micro operation? Give suitable examples of some four types of micro operations.--- (10 Marks)

3. (a) What do you mean by initialization of DMA controller? How DMA controller works? Explain with suitable block diagram. --- (10 Marks)

(b) What is virtual memory? Explain how virtual address is mapped to actual physical address. --- (10 Marks)

4. (a) Explain with an example, how effective address is calculated in different types of addressing modes. --- (10 Marks)

(b) Formulate a four segment instruction pipeline for a computer. Specify the operation to be performed in each segment. --- (10 Marks)

5. (a) Explain any two methods of hardwired control unit. --- (10 Marks)

(b) Explain the von newmann architecture with the help of diagram. --- (10 Marks)

6. (a) With neat flow chart, explain the procedure for division of floating point numbers carried out in a computer. --- (10 Marks)

(b) Explain the Flynn’s classification of parallel processing. --- (10 Marks)

7. Write short notes on any four: --- (20 Marks)

(a) PCI Bus architecture

(b) Systolic arrays

(c) Comparison of RISC and CISC

(d) IEEE 754 format

(e) Programmed I/O.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA), B.E. Computer Science (CS), Semester 4, December 2011.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA),

B.E. Computer Science (CS), Semester 4, December 2011.

Con.6904-11

MP-4108

(3 Hours)

[Total Mark: 100]

N. B.: (1) Question no 1 is compulsory.

(2) Attempt any four questions out of remaining six questions.

(3) Assume suitable data wherever necessary.

(4) Figures to the right indicate full marks.

1. (a) A block set- associative cache consists of 64 blocks divided in 4 block sets. The main memory contains 4096 blocks, each consisting of 128 words of 16 bit length:- --- (10 Marks)

(i) How many bits are there in main memory?

(ii) How many bits are there in each of the TAG, SET and WORD fields?

(b) Explain Static data flow computers and Dynamic data flow computer organization with diagram. --- (10 Marks)

2. (a) In two level memory, t_A1 = 10^-7S and t_AZ = 10^-2S. What must the hit ratio it be in order for the access efficiency to be at least 90% of its maximum possible value? --- (10 Marks)

(b) Write and explain the microprogram for LOAD AC. --- (10Marks)

3. (a) Perform division of the following numbers using restoring division: --- (10 Marks)

Dividend

=

17;

Divisor

=

03.

(b) Explain I/O processor and I/O channels with diagram. --- (10 Marks)

4. (a) Explain the floating point representation IEEE standard 754. --- (10 Marks)

(b) Explain Bus Arbitration Schemes with diagram. --- (10 Marks)

5. (a) Explain Array Processor with diagram. --- (10 Marks)

(b) Assume a magnetic disk has following characteristics: - --- (10 Marks)

I. 10,000 rpm spin rate

II. 2 ms head to head switching rate.

III. 3 ms T/T seek time.

IV. 5 platters, 1024 track per side, 50 sectors per track

V. Size of a sector is 512 bytes.

Compute: -

(i) Average capacity of disk

(ii) Average random access time

6. (a) What is locality of reference? Explain the different types of locality. Explain the performance characteristic of two level memory with respect to cost, access time and performance. --- (10 Marks)

(b) Explain the different mapping techniques of cache memory. --- (10 Marks)

7. Solve any four: - --- (20 Marks)

a) Write short notes on Inter-leaved memory

b) Explain difference between SRAM and DRAM.

c) RAID

d) Digital Versatile DISK (DVD)

e) Comparison of RISC and CISC.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA), B.E. Computer Science (CS), Semester 4, December 2010.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA),

B.E. Computer Science (CS), Semester 4, December 2010.

Con.5577-10

GT-6237

(3 Hours)

[Total Mark: 100]

N. B.: (1) Question no 1 is compulsory.

(2) Attempt any four questions out of remaining.

1. (a) Main memory has 3 pages and the processor requires pages from virtual memory in the following order.
23 2 1 5 2 4 5 3 25 2 Show the implementation of FIFO, LRU, LFU.--- (10 Marks)

(b) Explain SPARC Processor in detail. Draw and explain n bit windows architecture of SPARC processor. --- (10 Marks)

2. (a)Explain systolic processor with suitable examples. --- (10 Marks)

(b) What is cache memory? Explain cache coherence strategies in single and multiprocessor systems. --- (10 Marks)

3. (a) Compare and Contrast DMA, Programmed I/O. & interrupt driven I/O. – (10 Marks)

(b) What is RAID? Explain different RAID levels in detail. --- (10 Marks)

4. (a) Explain different bus arbitration schemes with suitable diagrams. --- (10 Marks)

(b) What is pipelining? Explain six stage instruction pipeline with suitable diagram. --- (10 Marks)

5. (a) Explain with suitable example booth’s algorithm. --- (10 Marks)

(b) Explain microinstructions, micro operations, micro- program in detail. --- (10 Marks)

6. (a) Explain RISC and CISC architectures in detail. --- (10 Marks)

(b) Explain Flynn’s classifications with suitable diagrams. Also comment on design issues of pipeline architecture. --- (10 Marks)

7. Write short notes on any Four: --- (20 marks)

1. PCI Bus
2. Memory Characteristics
3. Micro Instruction Sequencing and Execution
4. Loop Buffer
5. Interleaved Memory.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA), B.E. Computer Science (CS), Semester 4, May 2010.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA),

B.E. Computer Science (CS), Semester 4, May 2010.

Con.3022-10

AN-2506

(3 Hours)

[Total Mark: 100]

N. B.: (1) Question no 1 is compulsory.

(2) Solve any four questions out of remaining.

(3) Draw neat labelled diagram wherever necessary.

(4)Assume suitable data if required.

1.(a) Explain in detail characteristics of RISC and CISC. --- (10 Marks)

(b) Explain with suitable example booth s Algorithm for signed multiplication. --- (10 Marks)

2. (a) Explain Flynn’s classification in detail. --- (10 Marks)

(b) Define the term “soft wired and hardwired”. Explain with example the soft wired. --- (10 Marks)

3. (a) Explain with suitable example the difference between computer architecture and computer Organization. --- (10 Marks)

(b) Explain IEEE format for floating point number representation. --- (10 Marks)

4. (a) State the function of following CPU registers. --- (10 Marks)

MAR,

MDR,

IR,

PC,

SP.

(b) What is memory interleaving? Discuss various memory leaving techniques. --- (10 Marks)

5. (a) What is pipelining? Explain with suitable example the difference between serial executions and pipelined instruction execution. --- (10 Marks)

(b) Explain SPARC Processor. --- (10 Marks)

6. (a) Explain with state diagram MESI (Mutual Exclusive Shaved Invalid ) protocol. --- (10 Marks)

(b) Explain and solve the following problem using by non- restoring division algorithm. Hence divided 10/3. --- (10 Marks)

7. (a) Explain the different RAID levels.--- (10 Marks)

(b) Write short notes on: --- (10 Marks)

1. DMA
2. Vonneuman model in detail.