COMPUTER ORGANIZATION AND ARCHITECTURE (COA), B.E. Computer Science (CS), Semester 4, December 2012.

COMPUTER ORGANIZATION AND ARCHITECTURE (COA),

B.E. Computer Science (CS), Semester 4, December 2012.

Con.7412-12

KR-3632

(3 Hours)

[Total Mark: 100]

N. B.: (1) Question no 1 is compulsory.

(2) Attempt any four questions out of remaining six questions.

(3) Draw neat labelled diagram wherever necessary.

(4) Answer to each new question to be started on fresh page.

1. (a) Explain Van- Neumann Architecture. --- (6 Marks)

(b) Compare Computer Organization and Computer Architecture with Example. --- (4 Marks)

(c) Explain different Mapping techniques of cache Memory. --- (10 Marks)

2. (a) Compare and contrast DMA, programmed I/O and Interrupt driven I/O. ---(10 Marks)

(b) Compare SRAM and DRAM. ---(5 Marks)

(c) Compare RISC and CISC. --- (5 Marks)

3. (a) Explain design of control unit with respect to Soft wired and Hardwired approach. --- (10 Marks)

(b) Explain IEEE-754 standard formates to represent floating point numbers. --- (10 Marks)

4. (a) What is cache coherency? Explain different protocols to solve cache coherency. --- (10 Marks)

(b) Explain Non- Restoring division algorithm for performing 19/4. --- (10 Marks)

5. (a) Explain multiplication of signed numbers – 13* - 5 using Booth’s algorithm. --- (10 Marks)

(b) What is virtual memory? Explain role of paging and segmentation in virtual memory. --- (10 Marks)

6. (a) Explain SPARC processor in detail. --- (10 Marks)

(b) What is difference between pipelining and parallelism? Show that k – stage pipelined processor has k – times speed up as compared to non- pipelined system. --- (10 Marks)

7. Write short notes on following any four: ---- (20 Marks)

(a) Wave front Array

(b) RAID Memory

(c) Static and dynamic dataflow computer

(d) Systolic Processor

(e) I/O Processor and I/O Channels

(f) Characteristics of two level memory.