DIGITAL LOGIC DESIGN AND ANALYSIS (DLDA) MAY 2012 COMPUTER SCIENCE SEMESTER 3
Con. 4466 GN-8339(3 Hours) [Total Marks:-100]
N.B.: (1) Question No.1 is compulsory.
(2) Attempt any four from remaining from remaining questions.
(3) Figures to the right indicate full marks.
1. (a) Convert (54.45)10 into binary, base 4, octal and Hexadecimal Number Systems. [4 Marks]
(b) Subtract using 1's and 2's complement (15)10-(20)10. [4 Marks]
(c) Perform BCD addition of the decimal numbers 45 and 27. [4 Marks]
(d) Represent (25)10 in excess 3 and Gray code. [4 Marks]
(e) Perform:- i) (11001)2/(101)2 [4 Marks]
ii) (11001)2*(101)2
2. (a) Design a 4 bit binary to gray code converter. [10 Marks]
(b) Design a full Subtractor and implement using basic logic gates. [10 Marks]
3. (a) Simplify the following expression using Quine Mc-Cluskey method and implement with
universal gates only. [10 Marks]
F(A,B,C,D) = ∑M(1,3,4,5,6,7,9,11,12,13,14,15)
(b) Implement the following using only one 8:1 MUX. [10 Marks]
F(A,B,C,D) = ∑m(0,1,2,4,6,7,8,10,14,15)
4. (a) Design 2 bit digital magnitude comparator and implement using NAND gates
only. [10 Marks]
(b) Design a 32:1 multiplexer using 4:1 multiplexers. [10 Marks]
5. (a) Design a mod-6 synchronous counter using JK FF. [10 Marks]
(b) Covert: - [10 Marks]
i) SR FF to JK FF
ii) SR SR to D FF
6. (a) Draw a 4 bit ring counter. Draw the timing diagram and explain the working
of counter. [10 Marks]
(b) Explain the working of Universal shift register with the help of suitable
diagram. [10 Marks]
7. Write short notes on :-
(a) Error detecting and correcting codes. [5 Marks]
(b) TTL and CMOS. [5 Marks]
(c) ALU [5 Marks]
(d) DeMorgan's Theorems. [5 Marks]
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