DIGITAL LOGIC DESIGN AND ANALYSIS (DLDA) MAY 2011 COMPUTER SCIENCE SEMESTER 3

DIGITAL LOGIC DESIGN AND ANALYSIS (DLDA) MAY 2011 COMPUTER SCIENCE SEMESTER 3

                                       (3 Hours)                                   [Total Marks: -100]

1. (a) Convert (243.63)8 to decimal, binary and hexadecimal. [6 Marks]
    (b) Perform directly without converting to any other base- [6 Marks]
          (i) (BC 5)H - (A2B)H
         (ii) (210.2)4 + (312.2)4
         (iii) (56)8 x (45)8
    (c) Obtain hamming code for 1010. Prove that hamming code is an error detecting and
          correcting code. [8 Marks]

2. (a) Design a 3 bit binary to gray code converter. [10 Marks]
    (b) Design a full adder circuit using half adder and some gates. [10 Marks]

3. (a) Simplify using Q-M method and implement using NAND gates. [10 Marks]
                   f(A,B,C,D) = ∑m(4,5,8,9,11,12,13,15)
    (b) Implement the following expression using single 4:1 MUX. [10 Marks]
                  f(A,B,C,D) = ∑m(2,6,8,12,13,14)

4. (a) Design a 24 bit comparator using IC 7485. [10 Marks]
    (b) Design 1:28 line Demux using 1:8 Demux. [10 Marks]

5. (a) Design a synchronous counter using JK FF for following sequence:- [10 Marks] 
       
    (b) Convert JK FF to SR and D FF. [10 Marks]

6. (a) Draw a 3 bit ring counter and draw timing wave form. Prove that it is a divide by
         3 network. [10 Marks]
    (b) Explain the operation of 4 bit Universal shift register. [10 Marks]

7. Write short notes on: - [20 Marks]
      (a) Race around condition in JKFF.
      (b) TTL v/s CMOS
      (c) ALU
      (d) Priority encoder