DIGITAL LOGIC DESIGN AND ANALYSIS (DLDA) DECEMBER 2013 COMPUTER SCIENCE SEMESTER 3

DIGITAL LOGIC DESIGN AND ANALYSIS (DLDA) DECEMBER 2013 COMPUTER SCIENCE SEMESTER 3

Con. 8955-13                                                                                                   GX-12152

                                                    (3 Hours)                                            [Total Marks : -80]

N.B.: (1) Question No.1 is compulsory.
         (2) Solve any three questions from the remaining.
         (3) All questions carry equal marks.
         (4) Figures to the right indicate marks.
         (5) Assume suitable data if required.

1. (a) State De-morgan's Theorems. Convert the following (761.514)8 to binary and
          hexadecimal. [5 Marks]
    (b) Subtract the following using method given below: [5 Marks]
          (i) (11)10-(22)10 using 2's complement.
          (ii) (33)10-(44)10 using one's complement.
    (c) Write short note on Ring Counter using 'D' FF. [5 Marks]
    (d) Compare FPGA and CPLD. [5 Marks]

2. (a) Perform the following directly without converting to any other base. [5 Marks]
         (i) (63)8 * (21)8
         (ii) (D9)H - (80)H
     (b) (i) Simplify the boolean expression
            
           (ii) Express it is standard POS form
             
      (c) Simplify the logic function using K-map. [5 Marks]
            f(A,B,C,D) = ∑m(4,5,6,7,8,10,12) + d(2,9,11)
            Draw the logic diagram using NAND gates only.
       (d) Explain Astable multivibrator using op-amp with neat wave forms. [5 Marks]

3. (a) Design a sequence generator to generate the sequence using 'D' FF 1101001 and repeat.
         Draw neat state diagram and ckt.diagram. [10 Marks]
    (b) Implement the following logic function using all 4:1 multiplexers with select inputs as
         'B', 'C', 'D', 'E' only. [10 Marks]
          F(A,B,C,D,E) = ∑(0,1,3,6,8,9,10,13,15,17,20,24,30).
4. (a) Explain 3 bit Biodirectional shift register using JK Flip Flop. Draw the neat
         waveforms. [10 Marks]
    (b) What is FPGA. Explain basic architecture. What are its advantages over CPLD. [10 Marks]

5. (a) Design Full adder using 3:8 decoder with active low output and NAND gates. [5 Marks]
    (b) Use Quine Mc-Cluskey method to simplify the logic function as given below.
         F(A,B,C,D,E) = ∑m(0,1,8,10,11,12,20,21,30) + d(14, 19). Realize the above function
         using NAND gates. [15 Marks]

6. (a) Design mod-10 synchronous counter using JK Flip Flop. Check for the lock out condition.
         If so, how the lock out condition can be avoided? Draw the neat state diagram and circuit
         diagram with Flip Flops. [15 Marks] 
    (b) Explain the transfer characteristics of TTL NAND gate and hence define Fan-in and
         Fan-out. [5 Marks]