DIGITAL LOGIC DESIGN AND ANALYSIS (DLDA) MAY 2013 COMPUTER SCIENCE SEMESTER 3
(3 Hours) [Total Marks : -100]
N.B.: (1) Question No.1 is compulsory.
(2) Solve any four out of the remaining six question.
(3) Draw neat diagram whenever necessary.
1. (a) Convert (1234.56)10 to octal, hexadecimal. [4 Marks]
(b) Represent (29)10 into XS-3 and Gray code. [4 Marks]
(c) Design full adder using half adders. [4 Marks]
(d) Design a full subtractor using a decoder and additional gates. [4 Marks]
(e) Simplify and implement using gates. [4 Marks]
2. (a) What is canonical SOP and POS form? Explain with an example. [5 Marks]
(b) Implement the following using only one 8:1 MUX and few gate. [5 Marks]
F(A,B,C,D) = ∑m(0,3,5,7,9,13,15)
(c) Using the K-map method minimization technique simplify and draw the circuit for
the following function. [10 Marks]
F(A,B,C,D,E) = ∑m(0,1,2,3,4,5,7,8,9,11,14,16,17,18,19) +d(24,25)
3. (a) Simplify using Quine Mc-Cluskey method. Realize the equation using any universal
gate. [10 Marks]
F(A,B,C,D) = πM(0,2,3,6,7,8,9,12,13)
(b) Design a BCD adder using 4 bit binary adders and explain. [10 Marks]
4. (a) Design a 3 bit even and odd parity generator. [10 Marks]
(b) State truth table of 3 bit gray to binary conversion and design using 3:8 decoder and
additional gates. [10 Marks]
5. (a) Design MOD-6 synchronous counter and explain its operation. [10 Marks]
(b) Draw a 4 bit universal shift register and explain. [10 Marks]
6. (a) Design 4 bit ring counter using Jk ff, draw the timing diagram for the same. [10 Marks]
(b) Compare TTL and CMOS logic families.
Write notes on the following (any four) :- [20 Marks]
(a) ALU(Arithmatic Logic Unit)
(b) PAL and PLA
(c) Race around condition
(d) Error detecting and correcting code
(e) Applications of flip flops and registers
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