Friday, July 25, 2014

Microprocessors and Microcontollers - 1 (MPMC) Semester 5 (3 Hours) December 2010

Microprocessors and Microcontoll
Microprocessors and Microcontollers - 1 (MPMC)
Semester 5
(3 Hours) December 2010

 
GT-6762
[Total Marks : 100]
 
N.B: (1) Question no 1 is compulsory.  
  (2) Attempt any four question out of remaining six questions.  
       
1. (a) Interface 4K byte ROM and 8K byte R/W memory for 8085 based microcomputer system using (4K x 4) EPROM chips and RAM (2K x 8). Draw memory map, address bit map and exhaustive decoding logic circuit. 12
  (b) Write ALP to convert five packed BCD bytes to unpacked BCD bytes for 8085 based microcomputer. 08
       
2. (a) Draw and explain interrupt structure of 8085 microprocessor. 10
  (b) Write program to generate square wave of 1KHz on SOD pin of 8085 microprocessor. Also write delay subroutine using 8253 counter operate at 30KHz frequency. 10
       
3. (a) Draw and explain handshake mode of 8155 with suitable diagram. 10
  (b) Is it required to interface Eight Common anode seven segment display with 8085 through 8255 PPI. Draw interacting diagram and write ALP to display "WEL-DONE" Message. 10
       
4. (a) Draw and explain structure of TCON and TMOD SFR and explain it. 10
  (b) Explain PSW of 8051 Microcontroller with example for each Alog bit. 10
     
5. (a) Explain various addressing modes of ARM controller with suitable example. 10
  (b) Explain following instruction of ARM Controller :-
     (i) BCC up
     (ii) RSB Rd, Rs1, Rs2
     (iii) MLA  R4,  R3,  R2,  R6
     (iv) SWP R1, R2, [R3]
     (v) CDP P4, 3 C12, C13, C3, 4.
10
       
6. (a) Write program for 8051 microcontroller to multiple two 8 bit numbers stored in external memory locations 3000H and 3001H. Send the result on port 1and port 3. 10
  (b) Explain internal memory organization of 8051 microcontroller. 10
       
7. Write short notes on :- 20
  (a) Salient features of 89C51, 89C52, 89C2051 and 89C2052  
  (b) Stepper motor interfacing with 8051 microcontroller  
  (c) Memory access and branching instruction of RAM Controller.  

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