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Tuesday, June 24, 2014

ADVANCED MICROPROCESSOR (AMP) MAY 2012 COMPUTER SCIENCE SEMESTER 6

Con. 3999-12. GN-7208
(3 Hours) [Total Marks : 100]

N.B. : (1) Question No. 1 is compulsory.
(2) Out of remaining six questions, attempt any four questions.
(3) In all 5 questions to be attempted.
(4) Figures to the right indicate marks.

1. (a)	Enlist the instruction pairing rules of U and V pipeline in Pentium.	5
(b)	Write short note on Intel's Net burst micro architecture.	5
(c)	Draw the data flow graph for computation of integer power Z = Xn of an	5
	input number X.
(d)	State the use of following x 86 flags :	5
	RF, TF, VM, NT, IOPL.
2. (a)	Explain how the flushing of pipeline is minimized in Pentium architecture.	10
(b)	Explain in brief integer instruction pipeline stages of Pentium processor. List the	10
	steps instruction issue algorithm.
3. (a)	differentiate between Pentium and Pentium pro-processors wrt size of address/data	10
	bus, addressable memory virtual memory, L2 cache, generation, SMP support,
	integer pipeline stages, no. of integer pipes, floating point pipeline stages, no. of
	floating point pipes.
(b)	State the features of Intel ltanium processor. Draw the block diagram of ltanium	10
	processor and explain in brief.
4. (a)	Explain segmentation and paging in protected mode of 80386 processor.	10
(b)	Explain the Debug registers of 80386 DX processor.	10
5. (a)	Consider the following reservation table for a unifunction pipeline :-

	(i) Find the forbidden set of latencies	2
	(ii) State the collision vector	1
	(iii) Draw the state transition diagram	5
	(iv) List simple cycles and greedy cycles	1
	(v) Calculate MAL (minimal average latency).	1
(b)	Explain static data flow computer architecture with example.	10
6. (a)	Differentiate between real mode and protected mode of X 86 family.	10
(b)	Explain Cache organization of Pentium.	10
7.	Write short notes on :-
	(a) Structure of segment descriptor	5
	(b) USB	5
	(c) Layered architecture of SCSI	5
	(d) EISA.	5

ADVANCED MICROPROCESSOR (AMP) MAY 2011 COMPUTER SCIENCE SEMESTER 6

(3 Hours) [Total Marks: -100]

1. (a) Enlist the instruction pairing rules of 'U' and 'V' pipeline in pentium. [5 Marks]
(b) Write short note on: V-86 mode of operation. [5 Marks]
(c) State the features of Intel Itanium processor. [5 Marks]
(d) Explain the data types supported by SPARC architecture. [5 Marks]

2. (a) Explain with diagram arithmatic pipeline design for 8 bit multiplication. [10 Marks]
(b) What are the types of instructions hazards? Explain in detail. [10 Marks]

3. (a) Draw protected mode address translation mechanism in 80386DX with neat flow diagram.
Explain segment translation in detail. [10 Marks]
(b) State the use of following X86 flags: RF, TF, VM, NT, IOPL. [5 Marks]
(c) What is segment descriptor? Draw and explain the structure. [5 Marks]

4. (a) Explain how the flushing of pipeline problem is minimized in pentium architecture. [10 Marks]
(b) Write short note on the following: Branch Prediction Logic. [5 Marks]
(c) Explain different stages of floating point pipeline of pentium processor. [5 Marks]

5. (a) List the important features of pentium-II processor. Differentiate between pentium-II and
pentium-III. [10 Marks]
(b) Write short note on Intel's Net burst micro architecture. [5 Marks]
(c) Write the features of pentium-IV. [5 Marks]

6. (a) Explain the architecture of Super SPARC microprocessor with help of neat block
diagram. [10 Marks]
(b) Draw and explain various instruction formats of SPARC processor. [10 Marks]

7. Write short note on the following:- [20 Marks]
A) USB B) SCSI C) ISA D) EISA

Monday, June 23, 2014

ADVANCED MICROPROCESSOR (AMP) DECEMBER 2011 COMPUTER SCIENCE SEMESTER 6

1. (a)	Explain how flushing of pipeline problem is minimized in Pentium Architecture.	10
(b)	Draw protected mode address translation mechanism of 80386 DX with a neat	10
	diagram and explain the segment translation in detail.
2. (a)	Explain ltanium processor with respect to instruction format, core pipeline stages	10
	and its functionality in detail.
(b)	Explain the various data types supported by SPARC.	10
3. (a)	Explain the cache organisation of Pentium.	10
(b)	State features of PCI bus. Draw and explain work station based on PCI bus.	10
4. (a)	Differentiate between Pentium and Pentium Pro-processors with respect to	10
	generation, overlocking features, core pipeline stages, address bits, main memory
	size.
(b)	Draw and explain the state transition diagram for Pentium processor's bus cycle.	10
5. (a)	Explain the architecture of Super SPARC with the help of a neat diagram.	10
(b)	Explain instruction pairing rules of Pentium. Also explain the "Instruction Issue"	10
	algorithm in detail.
6. (a)	Explain ISA bus features in detail.	10
(b)	Explain floating point pipeline stages Pentium processor.	10
7.	Write short notes on the following :-	20
	(a) Intel Net Brust Microarchitecture
	(b) Structure of segment descriptor
	(c) SCSI
	(d) USB.

ADVANCED MICROPROCESSOR (AMP) DECEMBER 2010 COMPUTER SCIENCE SEMESTER 6

Con.5550-10 (REVISED COURSE) GT-7554

(3 Hours) [Total Marks :-100]

N.B: (1) Question No.1 is compulsory.
(2) Attempt any four questions out of remaining six questions.
(3) Each question have 20 marks.

1. (a) Explain Intel's Net Burst Micro-architecture with neat schematic. [10 Marks]
(b) Explain the protection mechanism of X86 intel family microprocessor. [10 Marks]
(c) Explain how the Linear Pipelining Working. [10 Marks]

2. (a) Differentiate between real mode and protected mode of X86 family. [10 Marks]
(b) State and explain operating mode of X86 family of processor. Show the mode transition
diagram highlighting important features. [10 Marks]
(c) Explain segment translation mechanism of X86 processor with flow chart. Also explain
segment descriptor field. [10 Marks]

3. (a) Explain different stages of integer pipeline and floating point pipeline of Pentium
Processor. [10 Marks]
(b) Explain Cache organisation of pentium. [10 Marks]
(c) Explain with block diagram how super scalar operation is carried but in pentium
processor. [10 Marks]

4. (a) Write the features of pentium IV processor. [10 Marks]
(b) Explain Itanium processor with respect to instruction format, core pipeline stages and the
functionality. [10 Marks]
(c) Explain the architecture of super SPARC microprocessor with the help of neat
diagram. [10 Marks]

5. (a) Data type supported by SPARC. [5 Marks]
(b) Register file of SPARC architecture. [5 Marks]
(c) Write short note on Ultra SPARC Processor. [5 Marks]
(d) Branch Prediction Logic. [5 Marks]

6. (a) Explain EFAG bits of pentium. [10 Marks]
(b) Explain the state transition diagram for pentium processor bus cycle. [10 Marks]
(c) Differentiated RISC and CISC. [10 Marks]

7. Write short notes on the following : -
(a) IDE [5 Marks]
(b) VESA [5 Marks]
(c) EISA [5 Marks]
(d) USB [5 Marks]

Saturday, June 21, 2014

ADVANCED MICROPROCESSOR (AMP) DECEMBER 2012 COMPUTER SCIENCE SEMESTER 6

Con. 8288-12. KR-8810
(3 Hours) [Total Marks : 100]
N.B. : (1) Question No. 1 is compulsory.
(2) Solve any four questions out of remaining six questions.
(3) Draw neat diagrams wherever necessary.

1. (a)	Draw and explain the block diagram of Hanium processor. Also expalin its salient	10
	features.
(b)	Explain the data cache organisation of Pentium.	10
2. (a)	Explain the floating point pipeline stages. Also explain the list of steps in instruction	10
	issue algorithm.
(b)	Explain how flushing of pipeline can be minimized in Pentium architecture. Also	10
	explain the instruction pairing rules for Pentium.
3. (a)	List and explain the important features of Pentium II processor. Also differentiate	10
	between Pentium II and Pentium III
(b)	Explain segmentation mechanism in 80386 DX and hence draw and explain the	10
	protected mode address translation mechanism in 80386 DX.
4. (a)	List the features of 8 bit, 18 bit and 32 bit EISA.	10
(b)	Draw and explain the work station based method of PCI bus and explain its	10
	features.
5. (a)	Explain the dynamic branch prediction logic in Pentium.	10
(b)	Draw and expalin the state transitions diagram for Pentium processor bus cycle.	10
6. (a)	Explain the debug register of Pentium.	10
(b)	Explain the protection mechanism in 386 DX via Callgates, Priviledge Levels.	10
7.	Write short notes on :-	20
	(a) Layered architecture of SCSI
	(b) USB
	(c) Dta types supported by SPARC
	(d) Architecture of Super SPARC

Friday, June 20, 2014

ADVANCED MICROPROCESSOR (AMP) May 2010 COMPUTER SCIENCE SEMESTER 6

Con.3500-10. (REVISED COURSE) AN-4477

(3 Hours) [Total Marks:-100]

N.B. (1) Question No.1 is compulsory.
(2) Attempt any four questions out of remaining six questions.

1. (a) Draw the block diagram of the 80386 DX processor and explain each block in brief. [10 Marks]
(b) Differentiate segmentation in real mode and in protected mode. [5 Marks]
(c) Explain how the flusing of pipeline problem in minimized in pentium architecture. [5 Marks]

2. (a) Enlist the instruction pairing rules for U and V pipeline in pentium. [5 Marks]
(b) List the steps of Instruction Issue Algorithm " in pentium. [5 Marks]
(c) Draw and explain pentium processor architecture. Highlight architectural features. [10 Marks]

3. (a) Explain dynamic branch prediction logic of pentium processor. [10 Marks]
(b) Differentiate between pentium and pentium pro-processor w.r.t generation, overclocking
feature, core pipelines stages, no. of transistors, address bits main memory size, L2 cache,
SMP support. [10 Marks]

4. (a) Compare super SPARC and ultra SPARC processors. Draw the architecture of super SPARC
and explain. [10 Marks]
(b) Draw and explain various instruction formats of SPARC processor. [10 Marks]

5. (a) Explain cache organisation of pentium. [10 Marks]
(b) State the features of PCI bus. Draw a work station based on PCI bus and explain. [10 Marks]

6. (a) List the features of each ISA bus version namely 8 bit, 16 bit and 32 bit EISA. [10 Marks]
(b) Explain floating point pipeline stages of pentium processor in brief. [10 Marks]

7. Write short notes on the following:- [20 Marks]
(a) Layered architecture of SCSI.
(b) USB
(c) Data types supported by SPARC
(d) Standard and burst bus cycles of pentium.

ADVANCED MICROPROCESSOR (AMP) May 2013 COMPUTER SCIENCE SEMESTER 6

Con. 7352-13. GS-9933
(3 Hours) [Total Marks : 100]

N.B. : (1) Question No. 1 is compulsory.
(2) Attempt any four questions out of remaining six questions.
(3) Draw neat labelled diagram wherever necessary.
(4) Answers to each new questions to be started on a fresh page.

1. (a)	Draw the block diagram of 80386 DX processor and explain each block in brief.	10
(b)	Differentiate segmentation in real mode and in protected mode.	5
(c)	Discuss the register set of 80386 processor.	5
2. (a)	What are the different types of instruction Hazards ? Explain in detail.	10
(b)	Draw and explain Pentium processor architecture.	10
3. (a)	Explain dynamic branch prediction logic of Pentium processor.	10
(b)	Explain different stages of Integer pipeline and floating point pipeline of Pentium	10
	processor.
4. (a)	Compare Super SPARC and Ultra SPARC processor. Draw and explain in brief	10
	the architecture of Super SPARC.
(b)	Explain the Itanium processor with respect to instruction format, core pipeline	10
	stages and the functionality.
5. (a)	Explain the Cache Organization of Pentium processor.	10
(b)	Draw and explain the state diagram of MESI transitions that occur within the.	10
	Pentium's data Cache memory.
6. (a)	Explain EFLAGS bits of Pentium.	10
(b)	State the features of PCI bus. Draw a work station based on PCI bus and explain.	10
7.	Write short notes on :- (any two)	20
	(a) Layered architecture of SCSI
	(b) USB
	(c) VESA.